As semiconductor processes advance to render increasingly smaller features, the design of dense, high-yielding (manufacturable) cells becomes increasingly challenging. See, e.g., U.S. Pat. No. 9,202,820, “Flip-flop, latch, and mux cells for use in a standard cell library and integrated circuits made therefrom,” to the inventor herein.
In the most advanced processes, patterning of critical layers is typically restricted to one direction (unidirectional) in each layer, delimited by cut masks, with the cut masks increasingly multi-patterned. In such technologies, careful attention to often non-obvious potential manufacturability problems is critical to successful implementation of a standard cell library. This inventor's prior U.S. Pat. No. 9,461,065 (“Standard cell library with DFM-optimized M0 cuts and V0 adjacencies”), incorporated by reference herein, provides an example of a DFM-optimized standard cell library for use in such advanced semiconductor processes.